The present invention relates to method and apparatus for testing a memory having plural memory cells and plural address latches.
It has been long recognized as desirable to provide built-in self test circuitry on a VLSI memory chip.
Such circuitry uses an algorithm such as the March test in which information is sequentially written to all of the memory cells of the array or of a section of the array, followed by reading the information, again in a sequence. Such algorithms typically require traversing the memory in the forward sequence for a number of times and then traversing the memory one or more times in a reverse sequence.
Circuitry for generating the address sequences in the prior art is inefficient partly because of the need to provide extra dedicated test circuitry for sequencing, and also because it is necessary to couple this sequencing circuitry into the conventional addressing circuitry used in the normal operating mode.
It would be desirable to provide sequencing circuitry which occupied less chip area than in the prior art and which was easier to couple into the conventional addressing circuitry.
According to a first aspect of the present invention there is provided a test circuit for a memory having plural memory cells and plural address latches responsive to addressing circuitry for reading from or writing to said memory cells in a normal mode, said test circuit having first connecting circuitry for connecting said address latches to form a linear feedback shift register, said linear feedback shift register being responsive to a clock signal to provide a first sequence of addresses for testing said memory in a test mode.
Preferably said linear feedback shift register is configured such that said first address sequence addresses substantially all of said memory cells.
Preferably said test circuit further comprises second connection circuitry for connecting said address latches to form a second linear feedback shift register responsive to said clock signal to provide a second sequence of addresses wherein said second sequence is the reverse of said first sequence.
According to a second aspect of the present invention there is provided a method of testing a memory having plural memory cells and plural address latches responsive to addressing circuitry for reading from or writing to said memory cells in a normal mode comprising:
connecting said address latches to form a linear feedback shift register;
clocking said linear feedback shift register to provide a first sequence of addresses;
using said first sequence of addresses to address said memory cells for testing thereof.